1. Field of the Invention
This invention relates to a method for manufacturing a liquid crystal display, and more particularly to a method for manufacturing a fringe field switching mode liquid crystal display capable of improving picture quality.
2. Description of the Related Art
As known in the art, the liquid crystal display (hereinafter xe2x80x9cLCDxe2x80x9d) mainly employs TN(twisted nematic) mode and STN(super twist nematic) mode as its operation mode. However, the TN and the STN mode LCDs have narrow viewing angle characteristics. The IPS(in-plan switching) mode has been proposed to improve the shortcoming of narrow viewing angle characteristics of the TN and the STN mode LCDs. The IPS mode LCD has a structure in that as a brief description, a pixel electrode and a counter electrode both for driving liquid crystal molecules are arranged in parallel on the same substrate so that an electric field is generated in-plane to the substrate plane.
The IPS mode LCD has an advantage of wider viewing angle than the TN or the STN mode LCD. However, the IPS mode LCD has a limitation of developments in the aspect of aperture ratio and transmittance since the pixel electrode and the counter electrode are made of opaque metal.
Accordingly, a high aperture ratio and high transmittance LCD switching with a fringe field(hereinafter xe2x80x9cFFS mode LCDxe2x80x9d) has been proposed to overcome the limits of aperture ratio and transmittance in the IPS mode LCD.
In the FFS mode LCD, a pixel electrode and a counter electrode are made of a transparent metal layer such as ITO, and the distance between those electrodes is narrower than that between upper and lower substrates. Consequently, when the FFS mode LCD is in operation, the fringe field is generated over the counter electrode and the pixel electrode thereby driving all the liquid crystal molecules existing over those electrodes. As a result, the FFS mode LCD obtains more enhanced aperture ratio and transmittance.
Hereinafter, a method for manufacturing a conventional FFS mode LCD will be discussed with reference to FIGS. 1 to 3. Herein, FIG. 1 is a cross-sectional view of a lower substrate of a thin film transistor portion in the FFS mode LCD, FIG. 2 is a cross-sectional view of a lower substrate of a pixel portion in the FFS mode LCD, and FIG. 3 is a cross-sectional view of a lower substrate of a pad portion in the FFS mode LCD.
A transparent insulating substrate 1 such as a glass substrate is provided. A transparent metal layer such as an ITO is deposited on the substrate 1, and then a counter electrode 2 is formed on the substrate 1 in shape of a comb or a plate by patterning the transparent metal layer according to a first mask process.
A first opaque metal layer is deposited on the substrate 1, and then a gate line 3, a common electrode line(not shown) and a pad 4 are formed by patterning the first opaque metal layer according to a second mask process. A gate insulating layer 5 is formed on a resultant as constructed above.
An un-doped amorphous silicon(hereinafter xe2x80x9ca-Sixe2x80x9d) layer and an SiN layer are deposited on the gate insulating layer 5 in turn, and then an etch stopper 6 is formed by patterning the SiN layer according to a third mask process. A doped amorphous silicon(hereinafter xe2x80x9cn+ a-Sixe2x80x9d) layer is deposited on the a-Si layer to cover the etch stopper 6, and then an ohmic contact layer 8 and a channel layer 7 are formed by patterning the n+ a-Si layer and the a-Si layer according to a fourth mask process.
A transparent metal layer such as the ITO is deposited on the resultant, and then a pixel electrode 9 is formed in shape of a comb by patterning the transparent metal layer according to a fifth mask process. Herein, when the counter electrode 2 is formed in shape of the comb, the pixel electrode 9 is disposed between the counter electrodes 2. The pad 4 is exposed by etching according to a sixth mask process the gate insulating layer portion that is disposed above the pad 4.
A second opaque metal layer is deposited on the resultant, and then a source electrode 10a, a drain electrode 10b and a data line 10 are formed by patterning the second opaque metal layer according to a seventh mask process. The data line 10 is contacted to the exposed pad 4. A passivation layer 20 made of SiN layer is deposited over the resultant, and then is patterned according to an eighth mask process so that a gate pad(not shown) and the data line portion in contact with the pad 4 is exposed.
Although not shown in the drawings, the lower substrate of the FFS mode LCD is completed by depositing a lower alignment layer on the resultant as constructed above. Afterward, the FFS mode LCD is accomplished by attaching the lower substrate an upper substrate in which an upper alignment layer is formed, with intervening a liquid crystal layer.
However, since the method for manufacturing the FFS mode LCD requires eight times of mask processes, manufacturing period and cost are increased thereby degrading productivity. That is, the mask process is a photolithography process, and the process itself includes the steps of resist-coating, exposing, developing, etching and resist-removing. Since one time of the mask process requires substantially long time, the eight times of mask processes require more time and cost. Accordingly, the foregoing conventional method for manufacturing FFS mode LCD incurs problems in the aspect of productivity.
Consequently, in order to solve the problems in the productivity, a manufacturing method for FFS mode LCD using the six times of mask processes has been recently proposed.
FIG. 4 is a cross-sectional view for showing a pixel portion in another conventional FFS mode LCD that has been manufactured according to the six times of mask processes, and the manufacturing method thereof will be described hereinafter.
A first transparent insulating substrate 40 is provided. A transparent metal layer such as an ITO is deposited on the substrate 40, and then a counter electrode 41 is formed by patterning the transparent metal layer according to a first mask process. A first opaque metal layer is deposited on a resultant, and then a gate line(not shown), a common electrode line(not shown) and a pad(not shown) are formed by patterning the first opaque metal layer according to a second mask process. A gate insulating layer 42 is formed on the resultant as constructed above.
An a-Si layer and an n+ a-Si layer are deposited in turn on the gate insulating layer 42, an active region of a thin film transistor is defined by patterning the n+ a-Si layer and the a-Si layer according to a third mask process. A second opaque metal layer is deposited on the resultant, and a data line including source and drain electrodes(not shown) is formed by patterning the second opaque metal layer according to a fourth mask process.
A passivation layer 43 is deposited on the entire resultant as constructed above, and then the passivation layer 43 is etched according to a fifth mask process to expose some portions of the pad and the drain electrode. The transparent metal layer such as the ITO is deposited on the passivation layer 43 so that the transparent metal layer is in contact with the exposed pad and the drain electrode. A pixel electrode 44 is formed by patterning the transparent metal layer according to the sixth mask process.
The reference symbols 45 and 55 not yet described in FIG. 4, are the lower alignment layer and the upper alignment layer respectively, and 50 refers to the upper transparent insulating substrate, 60 refers to the liquid crystal layer sandwiched between the substrates, and E1 and E2 are electric fields formed between the counter electrode 41 and the pixel electrode 44.
FIG. 5 is an equivalent circuit diagram illustrating the parasitic resistance and the parasitic capacitance in the electric field forming regions E1, E2. Referring to FIG. 5, the parasitic resistance and the parasitic capacitance (hereinafter referred to as xe2x80x9cthe parasitic impedancexe2x80x9d) in the first electric field forming region E1 includes parasitic impedance R45,C45 by the lower alignment layer 45, parasitic impedance R60,C60 by the liquid crystal layer 60, parasitic impedance R45,C45 by the lower alignment layer 45, parasitic impedance R43,C43 by the passivation layer 43 and parasitic impedance R42,C42, and they are serially connected to each other.
The parasitic impedance in the second electric field forming region E2 includes parasitic impedance R43,C43 by the passivation layer 43 and parasitic impedance R42,C42 by the gate insulating layer 42, and they are serially connected to each other.
As described above, the conventional manufacturing method for FFS mode LCD using the six times of mask processes has advantages in manufacturing time and cost by reducing two steps of mask processes, compared to the previous manufacturing method using the eight times of mask process.
However, since the pixel electrode is disposed at the passivation layer, the FFS mode LCD manufactured according to the six times of mask processes has a reduced number of layers existing at the first electric field forming region E1, compared to the number of layers at the FFS mode LCD manufactured according to the eight times of mask processes. As a result, the RC time constant in the FFS mode LCD is rather increased and picture quality thereof is degraded owing to the afterimages. The afterimages are generated when the residue DC is not easily discharged.
That is, the value of RC time constant is calculated by a product of resistance R and capacitance C as shown in the equation 1, and the equivalent capacitance Ceq to the serially connected capacitances can be calculated according to the equation 2.
Time constant=Rxc2x7Cxe2x80x83xe2x80x83equation 1
Ceq=1/(1/C1+1/C2+1/Cxe2x80x83xe2x80x83equation 2
Herein, from the equation 2, it is found that the sum of the capacitances is increased as the number of the serially connected capacitances increases. Accordingly, the decrease in the number of layers existing at the first electric field forming region E1 increases the RC constant, as a result the picture quality of the FFS mode LCD manufactured according to the six times of mask processes is degraded compared to that in the FFS mode LCD manufactured according to the eight times of mask processes, since RC constant is relatively larger.
Accordingly, the object of the present invention provides a method for manufacturing an FFS mode LCD capable of improving the productivity and picture quality.
To accomplish the foregoing object, a method for manufacturing the FFS mode LCD includes the steps of: depositing a transparent metal layer on a transparent insulating layer and forming a counter electrode by etching the transparent metal layer according to a first mask process; depositing an insulating layer on the counter electrode and the substrate; depositing a first opaque metal layer on the insulating layer and forming a gate line, a common electrode line and a pad by etching the first opaque metal layer according to a second mask process; depositing a gate insulating layer, an a-Si layer and an n+ a-Si layer in turn on a resultant and defining an active region of thin film transistor by etching the n+ a-Si layer and the a-Si layer according to a third mask process; depositing a transparent metal layer on the resultant and forming a pixel electrode of a comb shape by etching the transparent metal layer according to a fourth mask process; etching the gate insulating layer according to a fifth mask process so that the pad is exposed; forming a source electrode, a drain electrode and data line including a data pad by etching the second opaque metal layer according to a sixth mask process; and forming a passivation layer on the entire resultant and etching the passivation layer according to a seventh mask process so that the data pad is exposed.